The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating- point formats. The CVT16 instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set. CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007, which is supplemented by the XOP and FMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged. In recent documents, the name F16C is formally used in both Intel and AMD x86-64 architecture specifications.
Used for : AMD APU, AMD Athlon, AMD EPYC, AMD FX, AMD Opteron, AMD Ryzen, AMD Sempron, Intel Celeron, Intel Core i3, Intel Core i5, Intel Core i7, Intel Core i9, Intel Core M, Intel Pentium, Intel Xeon