Commentaar
High performance
—150 Dhrystone 2.1 MIPS @ 133 MHz
—235 Dhrystone 2.1 MIPS @ 206 MHz
Memory bus
—Interfaces to ROM, synchronous mask
ROM (SMROM), Flash, SRAM,
SRAM-like variable latency I/O,
DRAM, and synchronous DRAM (SDRAM)
—Supports two PCMCIA sockets
Low power (normal mode)
—<240 mW @1.55 V/133 MHz
—<400 mW @1.75 V/206 MHz
32-way set-associative caches
—16 Kbyte instruction cache
—8 Kbyte write-back data cache
Integrated clock generation
—Internal phase-locked loop (PLL)
—3.686-MHz oscillator
—32.768-kHz oscillator
32-entry MMUs
—Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
Power-management features
—Normal (full-on) mode
—Idle (power-down) mode
—Sleep (power-down) mode
Write buffer
—8-entry, between 1 and 16 bytes each
Big and little endian operating modes
Read buffer
—4-entry, 1, 4, or 8 words
3.3-V I/O interface
256 mini-ball grid array (mBGA)