Cyrix 486DRx²20/40
Cyrix 486DRx²16/32
Cyrix 486DRx²20/40
Cyrix 486DRx²25/50
Cyrix 486DRx²33/66
AMD EPYC 9654P
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Hersteller | AMD | ||
Modell | EPYC | ||
Architektur | x86 | ||
Code Name | Genoa | ||
Kernfrequenz (Nenn/Boost) | 2.4 GHz/3.7 GHz | ||
Kerne/Threads | 96/192 | ||
Paket / Sockel | FC-OLGA-6096 / Socket SP5 | ||
Physische Informationen | |||
Packungsgrösse | 7,54x7,2 cm | Herstellungsverfahren | 5 nm |
Die Größe (CPU+IGP) | 12x72.225+396.64 mm² | Transistoranzahl | 90000000000 |
Elektrische Informationen | |||
Busfrequenz | ??? | Core / Bus-Verhältnis | ??? |
Stromspannung | ??? | TDP | 360 W |
Caches | |||
L1-Cache (Daten) | 96x32 KB | L1 Cache (Anweisung) | 96x32 KB |
L2-Cache | 96x1024 KB | L3-Cache | 12x32768 KB |
Andere Informationen | |||
Veröffentlichungsdatum | |||
Startpreis | $10625 (OEM-Preis - für 1000 Teile) | ||
Funktionen / Merkmale |
16-bit Floating-Point conversion instructions (F16C) 3-operand Fused Multiply-Add instructions (FMA3) Advanced Vector Extensions (AVX) Advanced Vector Extensions 2 (AVX2) Advanced Vector Extensions 512 (AVX-512) Advanced Vector Extensions 512 BF16 (AVX-512 BF16) AES New Instructions AVX-512 Vector Neural Network Instructions (AVX512 VNNI) BMI Enhanced Virus Protection (EVP) MMX Pacifica Precision Boost 2 Pure Power Secure Boot Secure Encrypted Virtualization (SEV) Secure Hash Algorithm extensions (SHA) Secure Memory Encryption (SME) Secure Mode Execution Protection (SMEP) Simultaneous MultiThreading (SMT) SSE SSE2 SSE3 SSE4.1 SSE4.2 SSE4a SSSE3 Supervisor Mode Access Prevention (SMAP) x86-64 instructions |
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Integrierte Peripheriegeräte |
DDR5-4800 Speichercontroller 12 channels 128 lignes PCI-Express 5.0 Controller 64 lignes Contrôleur CXL1.1+ AMD Secure Processor (PSP) I2C Controller I3C Controller Serial-ATA 3.0 Controller USB3.2 Gen2 Host Controller SPI-Schnittstelle Allzweck-E / A-Pins High Speed UART |
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Artikelnummer | 100-000000803 (OEM, B1) | ||
Seltenheit | |||
In der Sammlung? | Nein | ||
Benchmarks |